## path
#FLOW_DDR_ROUTE = "/projects/tacoma12_a0/workspace/xwqiu/ddr_route/innovus_test/ddr_route_flow"
FLOW_DDR_ROUTE = "E:\\vscode\\gitee\\back_end\\DDR_ROUTE"
##

DDRPHY_L      = 539.04
DDRPHY_W      = 395.52

DDRPHY_H = "DDR_IO_SUBPHY_11_H"
DDRPHY_V = "DDR_IO_SUBPHY_11"
DDR_SYNC = "DDR_SYNC"

TERM_DDRPHY = ["WR_RSTB", "MC_PCK"]
TERM_SYNC   = ["PCK", "WR_RSTB", "PCK_HO"]

CORE_W        = 0.096
CORE_H        = 0.48
CORE_SIZE     = 5

SPACE_TO_PHY  = 25
SPACE_TO_SYNC = 4

SYNC_PT_X     = 609.499
SYNC_PT_Y     = 3333.12

DDR_TOP_FLOORPLAN_BOX_LLX = 0.0
DDR_TOP_FLOORPLAN_BOX_LLY = 0.0
DDR_TOP_FLOORPLAN_BOX_URX = 2301.024
DDR_TOP_FLOORPLAN_BOX_URY = 6198.72


ORI_ALL = ["N", "S", "W", "E", "FN", "FS", "FW", "FE"]


DDR_ROUTE_GAP_WIDTH = 2.88
DDR_ROUTE_BUF_WIDTH   = 3.84
DDR_ROUTE_BUF_HEIGHT  = 2.88

## routing

LEVEL_NUMBER  = 0
LEVEL_0_SPACE = 5

## DDRPHY group
DDRPHY_group = []
DDRPHY_group.append(["lg00_suffix", "lg01_suffix"])
DDRPHY_group.append(["lg02_suffix", "lg03_suffix"])
DDRPHY_group.append(["lg04_suffix", "lg05_suffix"])
DDRPHY_group.append(["lg06_suffix", "lg07_suffix"])
DDRPHY_group.append(["lg08_suffix", "lg09_suffix"])
DDRPHY_group.append(["lg10_suffix", "lg11_suffix"])
DDRPHY_group.append(["lg12_suffix", "lg13_suffix"])
DDRPHY_group.append(["lg14_suffix", "lg15_suffix"])


## GAP CORNER cell
GAP_CELL_H = "DDR_ROUTE_M8Y_M6_GAP_H_{}UM"
GAP_CELL_V = "DDR_ROUTE_M9Y_M7_GAP_V_{}UM"
CORNER_CELL = "DDRPHY_ROUTE_M9Y7_M8Y6_CON"
GAP_LENGTH = [100, 50, 10, 5, 2, 1]
GAP_WIDTH = 2.88
CORNER_LENGTH = 2.88
CORNER_WIDTH = 2.88